This invention relates to electrically-programmable semiconductor memories comprising a plurality of memory cells each having a charge-storage region (for example, a floating gate) whole charge state defines a memory state of the cell. The memories may be, for example, EEPROMs (electrically-erasable programmable read-only memories) or more simple EPROMs (electrically programmable read only memories) of various forms.
United Kingdom patent specification GB-A-1 425 985 describes electrically-programmable semiconductor memories comprising a plurality of memory cells, each cell having a field-effect transistor and a charge-storage region whose charge state defines a memory state of the cell. The known devices comprise a semiconductor body having for each cell a first insulating layer portion present at a major surface of the body over a first region of the body of a first conductivity type, the charge-storage region extending at a surface of the first insulating layer portion. There are programming means for each cell comprising an injector region of the opposite second conductivity type forming a p-n junction with the first region, and a control gate capacitively coupled to the charge-storage region.
Various forms of EPROMs are known using different injection mechanisms to inject charge-carriers (and especially hot electrons) into the first insulating layer portion to set the charge-state of the charge-storage region. In most currently used EPROM designs hot electrons are generated either by subjecting the drain or source of a MOS (insulated-gate field-effect) transistor with a floating gate to an avalanche breakdown or by applying sufficiently high fields to the transistor so that the hot electrons are generated in the channel itself. However, in these cases the electrons are most generally accelerated parallel to the surface of the body and so need to be redirected towards the surface to achieve more efficient injection into the charge-storage region. Furthermore, the doping profiles of the source and/or drain are adapted so as to generate sufficient hot electrons at reasonable voltage levels, and this may result in using a different MOS transistor process technology for the memory cells compared with what is desired for other parts of an integrated circuit device. If, for programming, hot electrons are used in the channel of the memory transistor, the source and drain geometries and/or doping may be optimized for this purpose in different ways, the read and write voltages being applied to different terminals of the memory transistor. Channel lengths shorter than those normally desired may be needed to program at low voltages. Alternatively, the memory cell may comprise two transistors of which the first transistor is used during reading and the second transistor is used during writing. This two-transistor arrangement may occupy a large space for the memory cell.
Another type of injector is known in which the hot electrons are generated by forward-biasing a diode. This diode may be inserted below the memory transistor, for example as described in GB-A-1 425 985. This form has several advantages including the possibility of using the same transistor process technology for the memory transistors as for other transistors in the circuit. However, it is necessary to generate a negative diode voltage in the circuit, and the diode also injects the electrons in all directions (including into the substrate) so that large substrate currents may be dissipated.